Sotabase

Career

· Researcher, Stanford University2024–
· Exchange Student, Chalmers University of Technology2003–2003
· Double B.A. in Computer Science and English, Brown University1999–1999
· Adjunct Lecturer in Engineering, Brown University
· Graduate Student, MIT
· Research Scientist, NVIDIA

Publications (102)

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach
Micro · 2018
329
cited
ExTensor: An Accelerator for Sparse Tensor Algebra
Micro · 2019
245
cited
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
IEEE Micro · 2020
211
cited
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
International Symposium on Computer Architecture · 2018
172
cited
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
International Symposium on High-Performance Computer Architecture · 2020
149
cited
Triggered instructions: a control paradigm for spatially-programmed architectures
International Symposium on Computer Architecture · 2013
135
cited
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
2011 IEEE 17th International Symposium on High Performance Computer Architecture · 2011
114
cited
Leap scratchpads: automatic memory and cache management for reconfigurable logic
Symposium on Field Programmable Gate Arrays · 2010
108
cited
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
89
cited
PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
Micro · 2014
71
cited
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
International Conference on Architectural Support for Programming Languages and Operating Systems · 2023
65
cited
INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design
Design Automation Conference · 2018
63
cited
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
International Conference on Architectural Support for Programming Languages and Operating Systems · 2016
62
cited
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA
International Conference on Formal Methods and Models for Co-Design · 2007
50
cited
Heracles: a tool for fast RTL-based design space exploration of multicore processors
Symposium on Field Programmable Gate Arrays · 2013
50
cited
CCICheck: Using μhb graphs to verify the coherence-consistency interface
Micro · 2015
47
cited
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
International Conference on Field-Programmable Logic and Applications · 2011
44
cited
MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators
arXiv.org · 2018
44
cited
ArMOR: Defending against memory consistency model mismatches in heterogeneous architectures
International Symposium on Computer Architecture · 2015
43
cited
Synthesis of synchronous assertions with guarded atomic actions
Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05. · 2005
42
cited
Sotabase
Michael Pellauer | Researcher Profile | Sotabase | Sotabase