Sotabase

Career

· Researcher, Stanford Security Lab2024–
· Distinguished Research Scientist, NVIDIA2022–2025
· Senior Research Scientist, NVIDIA2017–2022
· Senior Research Scientist, NVIDIA2015–2017
· Ph.D. in Electrical Engineering, Princeton University2015–
· Graduate Technical Intern, Intel2011–
· M.A. in Electrical Engineering, Princeton University2011–
· Graduate Student, Princeton University2009–2015
· B.S.E., University of Pennsylvania2009–
· Research Assistant, University of Pennsylvania2008–2009

Publications (92)

Nimble Page Management for Tiered Memory Systems
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
180
cited
Shared last-level TLBs for chip multiprocessors
2011 IEEE 17th International Symposium on High Performance Computer Architecture · 2011
145
cited
Triggered instructions: a control paradigm for spatially-programmed architectures
International Symposium on Computer Architecture · 2013
135
cited
The Relationship Between Working Alliance and Rehabilitation Outcomes
2002
127
cited
Psychological Well-Being: Its Relation to Work Personality, Vocational Identity, and Career Thoughts
The Journal of psychology · 2008
126
cited
Reducing GPU offload latency via fine-grained CPU-GPU synchronization
International Symposium on High-Performance Computer Architecture · 2013
123
cited
Causal Relationships Between Poverty and Disability
2007
90
cited
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
arXiv.org · 2018
82
cited
The Relationship Between Sense of Coherence and Adjustment in Persons with Disabilities
2000
78
cited
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests
Micro · 2018
77
cited
PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
Micro · 2014
71
cited
The working alliance: Rehabilitation outcomes for persons with severe mental illness
2004
70
cited
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs
TACO · 2013
70
cited
Translation Ranger: Operating System Support for Contiguity-Aware TLBs
International Symposium on Computer Architecture · 2019
70
cited
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface
International Conference on Architectural Support for Programming Languages and Operating Systems · 2016
64
cited
The Relationship Between Sense of Coherence and Career Thoughts
2002
64
cited
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
International Conference on Architectural Support for Programming Languages and Operating Systems · 2016
62
cited
Trauma symptoms: Relationship with career thoughts, vocational identity, and developmental work personality
2006
57
cited
CCICheck: Using μhb graphs to verify the coherence-consistency interface
Micro · 2015
47
cited
Family Coping in Families with a Child with a Disability
Education and Training in Mental Retardation and Developmental Disabilities · 2002
47
cited
Sotabase
Daniel Lustig | Researcher Profile | Sotabase | Sotabase