Sotabase

Career

· Associate Professor, UC Berkeley2024–
· Assistant Professor, UC Berkeley2019–2024
· Senior Research Scientist, NVIDIA2018–2019
· Research Intern, IBM T.J. Watson Research Center2015–2015
· Research Intern, Intel Labs2012–2012
· MS in Computer Science, Harvard University2009–2014
· PhD in Computer Science, Harvard University2009–2016
· Bachelor of Electrical Engineering, Zhejiang University2005–2009

Publications (68)

Timeloop: A Systematic Approach to DNN Accelerator Evaluation
IEEE International Symposium on Performance Analysis of Systems and Software · 2019
588
cited
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Micro · 2019
439
cited
KVQuant: Towards 10 Million Context Length LLM Inference with KV Cache Quantization
Neural Information Processing Systems · 2024
391
cited
MachSuite: Benchmarks for accelerator design and customized architectures
IEEE International Symposium on Workload Characterization · 2014
317
cited
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
IEEE Micro · 2020
315
cited
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
Design Automation Conference · 2019
307
cited
RETROSPECTIVE: Aladdin: a Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures
2023
180
cited
Co-designing accelerators and SoC interfaces using gem5-Aladdin
Micro · 2016
160
cited
Full Stack Optimization of Transformer Inference: a Survey
arXiv.org · 2023
152
cited
Energy characterization and instruction-level energy model of Intel's Xeon Phi processor
International Symposium on Low Power Electronics and Design · 2013
132
cited
MAGNet: A Modular Accelerator Generator for Neural Networks
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · 2019
130
cited
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
International Symposium on Computer Architecture · 2021
129
cited
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
IEEE Journal of Solid-State Circuits · 2020
93
cited
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
89
cited
ISA-independent workload characterization and its implications for specialized architectures
IEEE International Symposium on Performance Analysis of Systems and Software · 2013
79
cited
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures
arXiv.org · 2019
73
cited
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
IEEE Journal of Solid-State Circuits · 2021
70
cited
INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design
Design Automation Conference · 2018
63
cited
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
Symposium on VLSI Circuits · 2019
51
cited
SPEED: Speculative Pipelined Execution for Efficient Decoding
arXiv.org · 2023
49
cited
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Yakun Sophia Shao | Researcher Profile | Sotabase | Sotabase