Sotabase

Career

· Senior Distinguished Research Scientist, Nvidia2014–
· Doctorate in Electrical Engineering, University of Illinois1979–1979
· Master of Science in Electrical Engineering, Purdue University1975–1975
· Bachelor of Science in Electrical Engineering, Purdue University1974–1974
· Compaq
· Digital Equipment Corporation (DEC)
· Intel Fellow and Director of Microarchitecture Research, Intel
· Professor of the Practice, Electrical Engineering and Computer Science Department (EECS), MIT

Publications (363)

Efficient Processing of Deep Neural Networks: A Tutorial and Survey
Proceedings of the IEEE · 2017
3,408
cited
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
IEEE Journal of Solid-State Circuits · 2016
2,669
cited
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
International Symposium on Computer Architecture · 2016
1,576
cited
SCNN: An accelerator for compressed-sparse convolutional neural networks
International Symposium on Computer Architecture · 2017
1,212
cited
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. · 2003
1,058
cited
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 2018
953
cited
Adaptive insertion policies for high performance caching
International Symposium on Computer Architecture · 2007
751
cited
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
IEEE International Symposium on Performance Analysis of Systems and Software · 2019
588
cited
Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications
International Conference for High Performance Computing, Networking, Storage and Analysis · 2017
552
cited
The soft error problem: an architectural perspective
International Symposium on High-Performance Computer Architecture · 2005
476
cited
Simultaneous multithreading: a platform for next-generation processors
IEEE Micro · 1997
460
cited
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Micro · 2019
439
cited
There’s plenty of room at the Top: What will drive computer performance after Moore’s law?
Science · 2020
376
cited
RETROSPECTIVE: High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)
2023
373
cited
RETROSPECTIVE: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
2023
368
cited
Memory dependence prediction using store sets
Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235) · 1998
363
cited
Adaptive insertion policies for managing shared caches
International Conference on Parallel Architectures and Compilation Techniques · 2008
325
cited
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors
Micro · 2018
312
cited
Techniques to reduce the soft error rate of a high-performance microprocessor
Proceedings. 31st Annual International Symposium on Computer Architecture, 2004. · 2004
299
cited
SHiP: Signature-based Hit Predictor for high performance caching
Micro · 2011
283
cited
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