Sotabase

Career

· Assistant Professor, MIT EECS2024–
· Assistant Professor, Massachusetts Institute of Technology (MIT)2019–
· Assistant Professor, MIT Electrical Engineering and Computer Science Department2018–
· Member of the Model-Based Embedded and Robotics Systems Group, MIT CSAIL

Publications (44)

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
Micro · 2018
283
cited
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures
USENIX Security Symposium · 2018
274
cited
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
IEEE Micro · 2019
213
cited
Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World
IEEE Symposium on Security and Privacy · 2019
197
cited
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
International Symposium on Computer Architecture · 2018
172
cited
Secure hierarchy-aware cache replacement policy (SHARP): Defending against cache-based side channel attacks
International Symposium on Computer Architecture · 2017
122
cited
PACMAN: Attacking ARM Pointer Authentication With Speculative Execution
IEEE Micro · 2022
86
cited
MicroScope: Enabling Microarchitectural Replay Attacks
IEEE Micro · 2020
78
cited
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay
Micro · 2016
57
cited
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
Micro · 2020
49
cited
SpecTaint: Speculative Taint Analysis for Discovering Spectre Gadgets
Network and Distributed System Security Symposium · 2021
48
cited
Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects
USENIX Security Symposium · 2022
35
cited
SecDir: A Secure Directory to Defeat Directory Side-Channel Attacks
International Symposium on Computer Architecture · 2019
30
cited
Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis
Micro · 2020
27
cited
There’s Always a Bigger Fish: A Clarifying Analysis of a Machine-Learning-Assisted Side-Channel Attack
IEEE Micro · 2022
25
cited
Pensieve: Microarchitectural Modeling for Security Evaluation
International Symposium on Computer Architecture · 2023
23
cited
DAGguise: mitigating memory timing side channels
International Conference on Architectural Support for Programming Languages and Operating Systems · 2022
22
cited
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum)
Micro · 2019
19
cited
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes
International Symposium on Computer Architecture · 2023
15
cited
Record-Replay Architecture as a General Security Framework
International Symposium on High-Performance Computer Architecture · 2018
13
cited
Sotabase
Mengjia Yan | Researcher Profile | Sotabase | Sotabase