Sotabase

Career

· Academic Consultant, CPU Design Verification Team, NVIDIA2025–2025
· Consultant, SEG Formal Verification Team, Apple Inc.2022–2022
· Assistant Professor of Computer Science and of Electrical Engineering, Stanford University2020–
· Research Scientist, FAIR SysML, Facebook2019–2020
· Graduate Research Intern, Architecture Research Group, NVIDIA2016–
· Verification Graduate Intern, P-Series Verification Group, IBM2013–
· MA, Computer Science, Princeton University2013–2015
· PhD in Computer Science, Princeton University2013–2019
· Research Assistant, Computer Science Department, Princeton University2013–2019
· Undergraduate Technical Intern, FEV/DFT Group, Intel2012–
· Undergraduate Intern, Continuous Improvement Group, Blue Cross Blue Shield2011–
· BS, Computer Engineering, Purdue University2009–2013

Publications (42)

RecSSD: near data processing for solid state drive based recommendation inference
International Conference on Architectural Support for Programming Languages and Operating Systems · 2021
127
cited
nl2spec: Interactively Translating Unstructured Natural Language to Temporal Logics with Large Language Models
International Conference on Computer Aided Verification · 2023
105
cited
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
arXiv.org · 2018
82
cited
RecShard: statistical feature-based memory optimization for industry-scale neural recommendation
International Conference on Architectural Support for Programming Languages and Operating Systems · 2022
78
cited
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests
Micro · 2018
77
cited
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
International Conference on Architectural Support for Programming Languages and Operating Systems · 2016
62
cited
Opening Pandora’s Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data
International Symposium on Computer Architecture · 2021
51
cited
Porcupine: a synthesizing compiler for vectorized homomorphic encryption
ACM-SIGPLAN Symposium on Programming Language Design and Implementation · 2021
50
cited
ArMOR: Defending against memory consistency model mismatches in heterogeneous architectures
International Symposium on Computer Architecture · 2015
43
cited
CPR: Understanding and Improving Failure Tolerant Training for Deep Learning Recommendation with Partial Recovery
Conference on Machine Learning and Systems · 2020
41
cited
Axiomatic hardware-software contracts for security
International Symposium on Computer Architecture · 2022
34
cited
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings
arXiv.org · 2016
29
cited
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach
IEEE Micro · 2019
26
cited
Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations
Micro · 2021
23
cited
Analysis and Mitigations of Reverse Engineering Attacks on Local Feature Descriptors
arXiv.org · 2021
16
cited
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time
IEEE Symposium on Security and Privacy · 2023
16
cited
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification
Formal Methods in Computer-Aided Design · 2018
15
cited
Model Selection for Latency-Critical Inference Serving
European Conference on Computer Systems · 2024
13
cited
Translating Natural Language to Temporal Logics with Large Language Models and Model Checkers
Formal Methods in Computer-Aided Design · 2024
11
cited
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation
arXiv.org · 2025
11
cited
Sotabase
Caroline Trippel | Researcher Profile | Sotabase | Sotabase