Sotabase

Career

· Associate Professor, UC Berkeley2025–
· Associate Professor, University of California, Berkeley2024–
· Associate Professor, University of Illinois at Urbana-Champaign2023–2023
· Assistant Professor, University of Illinois at Urbana-Champaign2017–2023
· Research Post-Doc, NVIDIA2016–2017
· Instructor, Teaching Assistant, Massachusetts Institute of Technology (MIT)2012–2013
· S.M., Massachusetts Institute of Technology (MIT)2012–2013
· Doctor of Philosophy (Ph.D.), Massachusetts Institute of Technology (MIT)2010–2016
· Research Assistant, Massachusetts Institute of Technology (MIT)2010–2016
· Intern, Oracle2008–
· Research Assistant, UC Berkeley2008–2010
· Bachelor's degree, University of California, Berkeley2008–2010
· Teaching Assistant, Lab Assistant, Grader, UC Berkeley2007–2010

Publications (143)

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
Micro · 2018
283
cited
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures
USENIX Security Symposium · 2018
274
cited
ExTensor: An Accelerator for Sparse Tensor Algebra
Micro · 2019
245
cited
ZeroTrace : Oblivious Memory Primitives from Intel SGX
Network and Distributed System Security Symposium · 2018
238
cited
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
IEEE Micro · 2019
213
cited
A secure processor architecture for encrypted computation on untrusted programs
Scalable Trusted Computing · 2012
203
cited
Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World
IEEE Symposium on Security and Privacy · 2019
197
cited
Constants Count: Practical Improvements to Oblivious RAM
USENIX Security Symposium · 2015
197
cited
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
International Symposium on Computer Architecture · 2018
172
cited
Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM
Theory of Cryptography Conference · 2016
164
cited
Design space exploration and optimization of path oblivious RAM in secure processors
International Symposium on Computer Architecture · 2013
157
cited
Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86
IEEE Micro · 2023
127
cited
PyTorchFI: A Runtime Perturbation Tool for DNNs
2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) · 2020
124
cited
Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical
USENIX Security Symposium · 2021
118
cited
Mind mappings: enabling efficient algorithm-accelerator mapping space search
International Conference on Architectural Support for Programming Languages and Operating Systems · 2021
110
cited
Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM
International Conference on Architectural Support for Programming Languages and Operating Systems · 2015
105
cited
Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing
IACR Cryptology ePrint Archive · 2018
103
cited
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
International Symposium on High-Performance Computer Architecture · 2014
102
cited
Speculative interference attacks: breaking invisible speculation schemes
International Conference on Architectural Support for Programming Languages and Operating Systems · 2020
90
cited
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
89
cited
Sotabase