Sotabase

Career

· Professor Of Computer Science, Georgia Institute of Technology2020–
· Professor Of Electrical And Computer Engineering, Georgia Institute of Technology2018–2020
· Associate Professor Of Electrical And Computer Engineering, Georgia Institute of Technology2011–2018
· Research Scientist, IBM T. J. Watson Research Center NY2007–2011
· IC Design Engineer, Texas Instruments (India)2001–2001

Publications (135)

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
Micro · 2006
1,087
cited
Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling
Micro · 2009
756
cited
Adaptive insertion policies for high performance caching
International Symposium on Computer Architecture · 2007
751
cited
Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers
International Conference on Architectural Support for Programming Languages and Operating Systems · 2018
420
cited
A Case for MLP-Aware Cache Replacement
International Symposium on Computer Architecture · 2006
335
cited
Adaptive insertion policies for managing shared caches
International Conference on Parallel Architectures and Compilation Techniques · 2008
325
cited
Accelerating critical section execution with asymmetric multi-core architectures
International Conference on Architectural Support for Programming Languages and Operating Systems · 2009
316
cited
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
International Symposium on High-Performance Computer Architecture · 2010
291
cited
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
Micro · 2012
273
cited
CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping
Micro · 2018
261
cited
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
International Symposium on High-Performance Computer Architecture · 2016
240
cited
The V-Way cache: demand-based associativity via global replacement
International Symposium on Computer Architecture · 2005
239
cited
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
International Conference on Architectural Support for Programming Languages and Operating Systems · 2008
221
cited
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks · 2015
212
cited
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
International Symposium on Computer Architecture · 2013
187
cited
Morphable memory system: a robust architecture for exploiting multi-level phase change memories
International Symposium on Computer Architecture · 2010
186
cited
MAZE: Data-Free Model Stealing Attack Using Zeroth-Order Gradient Estimation
Computer Vision and Pattern Recognition · 2020
181
cited
NVRAM-aware Logging in Transaction Systems
Proceedings of the VLDB Endowment · 2014
163
cited
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
Micro · 2014
161
cited
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
International Symposium on Computer Architecture · 2012
160
cited
Sotabase