Sotabase

Career

· Assistant Professor, University of Toronto2023–
· Postdoctoral Researcher, NVIDIA Research2022–2023
· Doctor of Philosophy (Ph.D.) in Computer Engineering, Georgia Institute of Technology2016–2022
· PhD Student, Georgia Institute of Technology2016–2022
· B.Tech and M.Tech, Indian Institute of Technology - Bombay
· Assistant Prof, CS, University of Toronto

Publications (41)

CleanupSpec: An "Undo" Approach to Safe Speculation
Micro · 2019
136
cited
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories
Micro · 2018
101
cited
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
USENIX Security Symposium · 2020
100
cited
Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows
International Conference on Architectural Support for Programming Languages and Operating Systems · 2022
96
cited
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
International Symposium on High-Performance Computer Architecture · 2018
94
cited
Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking
International Symposium on Computer Architecture · 2022
81
cited
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
International Symposium on High-Performance Computer Architecture · 2022
61
cited
AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime
Micro · 2022
60
cited
Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion
International Conference on Architectural Support for Programming Languages and Operating Systems · 2021
49
cited
SQUIP: Exploiting the Scheduler Queue Contention Side Channel
IEEE Symposium on Security and Privacy · 2023
33
cited
Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning
Seed · 2021
26
cited
PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks
Dependable Systems and Networks · 2023
26
cited
PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers
International Symposium on Computer Architecture · 2024
24
cited
HeapCheck: Low-cost Hardware Support for Memory Safety
ACM Transactions on Architecture and Code Optimization (TACO) · 2022
21
cited
Practical Timing Side-Channel Attacks on Memory Compression
IEEE Symposium on Security and Privacy · 2021
18
cited
Hardware Support to Improve Fuzzing Performance and Precision
Conference on Computer and Communications Security · 2021
15
cited
QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues
International Symposium on High-Performance Computer Architecture · 2025
14
cited
GPUHammer: Rowhammer Attacks on GPU Memories are Practical
USENIX Security Symposium · 2025
11
cited
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping
IEEE computer architecture letters · 2023
11
cited
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation
arXiv.org · 2024
10
cited
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Gururaj Saileshwar | Researcher Profile | Sotabase | Sotabase