Sotabase

Career

· Professor and Associate Chair of SCS, Georgia Institute of Technology2019–
· Graduate Technical Intern, Intel Corporation2006–2006
· MSE in Electrical and Computer Engineering, University of Texas at Austin2001–2003
· Ph.D. in Electrical and Computer Engineering, University of Texas at Austin2001–2007
· Visiting Researcher, Hyundai Motor Company1998–1999
· MS in Mechanical Engineering, Seoul National University1996–1998
· BS in Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST)1992–1996

Publications (53)

Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing
USENIX Security Symposium · 2016
528
cited
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
2007 IEEE 13th International Symposium on High Performance Computer Architecture · 2007
370
cited
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
International Symposium on High-Performance Computer Architecture · 2017
290
cited
A performance analysis framework for identifying potential benefits in GPGPU applications
ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming · 2012
229
cited
CAIRO
ACM Transactions on Architecture and Code Optimization (TACO) · 2017
153
cited
When Prefetching Works, When It Doesn’t, and Why
TACO · 2012
146
cited
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Micro · 2010
141
cited
Techniques for efficient processing in runahead execution engines
International Symposium on Computer Architecture · 2005
117
cited
Distributed Perception by Collaborative Robots
IEEE Robotics and Automation Letters · 2018
82
cited
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
IEEE Micro · 2006
74
cited
Toward Collaborative Inferencing of Deep Neural Networks on Internet-of-Things Devices
IEEE Internet of Things Journal · 2020
73
cited
Address-value delta (AVD) prediction: increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns
Micro · 2005
56
cited
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
International Symposium on Computer Architecture · 2007
52
cited
Wish branches: combining conditional branching and predication for adaptive predicated execution
Micro · 2005
48
cited
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
IEEE computer architecture letters · 2005
44
cited
FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion
International Symposium on Computer Architecture · 2012
38
cited
Musical Chair: Efficient Real-Time Recognition Using Collaborative IoT Devices
arXiv.org · 2018
36
cited
Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)
Synthesis Lectures on Computer Architecture · 2012
36
cited
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
Micro · 2006
35
cited
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
International Conference on Architectural Support for Programming Languages and Operating Systems · 2008
33
cited
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