Sotabase

Career

· Assistant Professor in Computer Science, University of Illinois Urbana-Champaign2021–
· Special Faculty Systems Scientist in Electrical and Computer Engineering, Carnegie Mellon University2016–2020
· Postdoctoral Research Associate in Electrical and Computer Engineering, Carnegie Mellon University2014–2016
· Graduate student in M3 Architecture Group, Computer Systems Laboratory, Cornell University

Publications (117)

Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
International Conference on Architectural Support for Programming Languages and Operating Systems · 2018
358
cited
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives
Proceedings of the IEEE · 2017
306
cited
Processing Data Where It Makes Sense: Enabling In-Memory Computation
Microprocessors and microsystems · 2019
285
cited
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
International Symposium on High-Performance Computer Architecture · 2016
240
cited
A Modern Primer on Processing in Memory
arXiv.org · 2020
236
cited
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
ICCD · 2016
219
cited
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks · 2015
215
cited
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Measurement and Modeling of Computer Systems · 2016
208
cited
Understanding Reduced-Voltage Operation in Modern DRAM Devices
Measurement and Modeling of Computer Systems · 2017
205
cited
MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices
USENIX Conference on File and Storage Technologies · 2018
201
cited
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
BMC Genomics · 2017
197
cited
SIMDRAM: a framework for bit-serial SIMD processing using DRAM
International Conference on Architectural Support for Programming Languages and Operating Systems · 2021
189
cited
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
IEEE computer architecture letters · 2017
187
cited
Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions
Briefings Bioinform. · 2017
185
cited
Processing-in-memory: A workload-driven perspective
IBM Journal of Research and Development · 2019
171
cited
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
International Symposium on High-Performance Computer Architecture · 2021
165
cited
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
Measurement and Modeling of Computer Systems · 2018
159
cited
Design-Induced Latency Variation in Modern DRAM Chips
Proceedings of the ACM on Measurement and Analysis of Computing Systems · 2017
149
cited
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Micro · 2020
144
cited
Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes
Micro · 2017
139
cited
Sotabase