Sotabase

Career

· Senior Hardware Engineer, Microsoft2022–
· Graduate Student, Georgia Institute of Technology2013–2019
· Microsoft

Publications (16)

DEUCE: Write-Efficient Encryption for Non-Volatile Memories
International Conference on Architectural Support for Programming Languages and Operating Systems · 2015
145
cited
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems
Micro · 2018
56
cited
DICE: Compressing DRAM caches for bandwidth and capacity
International Symposium on Computer Architecture · 2017
43
cited
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
International Symposium on Computer Architecture · 2018
38
cited
SHiP + + : Enhancing Signature-Based Hit Predictor for Improved Cache Performance
2017
29
cited
Enabling Transparent Memory-Compression for Commodity Memory Systems
International Symposium on High-Performance Computer Architecture · 2019
28
cited
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems
ICCD · 2019
14
cited
CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement
arXiv.org · 2018
8
cited
Towards Bandwidth-Efficient Prefetching with Slim AMPM
2015
8
cited
Calipers: a criticality-aware framework for modeling processor performance
International Conference on Supercomputing · 2022
7
cited
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
ICCD · 2019
4
cited
DICE
2017
3
cited
Write Prediction for Persistent Memory Systems
International Conference on Parallel Architectures and Compilation Techniques · 2021
2
cited
HoPE
ACM Trans. Design Autom. Electr. Syst. · 2017
1
cited
Memory Controller Metadata Cache : Compressibility & Location Info CoreLLC Compression-Decompression Engine DRAM Metadata Processor
2018
Table of Contents
Animal - science proceedings · 2021
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