Sotabase

Career

· Professor, University of California, Berkeley, Department of EECS1999–
· Electronics Engineer, Silicon Systems, Inc., Texas Instruments Storage Products Group1996–
· Lecturer in electronics courses, University of Belgrade1992–

Publications (288)

Digital Integrated Circuits
2003
1,025
cited
Improved sense-amplifier-based flip-flop: design and measurements
IEEE Journal of Solid-State Circuits · 2000
488
cited
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
IEEE Micro · 2020
315
cited
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
Design Automation Conference · 2019
307
cited
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
IEEE Journal of Solid-State Circuits · 2004
270
cited
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
International Symposium on Computer Architecture · 2018
244
cited
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
IEEE Transactions on Very Large Scale Integration (vlsi) Systems · 2000
215
cited
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters
IEEE Transactions on Circuits and Systems Part 1: Regular Papers · 2004
208
cited
Analysis of Absorbing Sets and Fully Absorbing Sets of Array-Based LDPC Codes
IEEE Transactions on Information Theory · 2009
207
cited
Methods for true energy-performance optimization
IEEE Journal of Solid-State Circuits · 2004
200
cited
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS
IEEE Journal of Solid-State Circuits · 2013
190
cited
IEEE Transactions on Circuits and Systems II: Express Briefs
2004
189
cited
Analysis and design of low-energy flip-flops
ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) · 2001
185
cited
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
Design, Automation and Test in Europe · 2020
182
cited
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003
175
cited
Large-Scale SRAM Variability Characterization in 45 nm CMOS
IEEE Journal of Solid-State Circuits · 2009
173
cited
FinFET-based SRAM design
ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. · 2005
170
cited
VLSI architectures for iterative decoders in magnetic recording channels
2001
166
cited
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors
IEEE Journal of Solid-State Circuits · 2010
164
cited
High throughput low-density parity-check decoder architectures
GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270) · 2001
141
cited
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Borivoje Nikolic | Researcher Profile | Sotabase | Sotabase