Sotabase

Career

· Assistant Professor, University of California, Berkeley2024–
· PhD in Computer Science, University of California, Berkeley2019–2024
· PhD in Computer Science, UC Berkeley2018–2024
· MS in Computer Science, University of California, Berkeley2018–2024
· B.S. in Electrical Engineering and Computer Sciences, University of California, Berkeley2015–2018
· Research Intern, Google
· Graduate Student Instructor, University of California, Berkeley

Publications (29)

The Rocket Chip Generator
2016
762
cited
This Paper Is Included in the Proceedings of the 12th Usenix Symposium on Operating Systems Design and Implementation (osdi '16). Network Requirements for Resource Disaggregation Network Requirements for Resource Disaggregation
385
cited
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
IEEE Micro · 2020
315
cited
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
International Symposium on Computer Architecture · 2018
244
cited
BOSS: Building Operating System Services
Symposium on Networked Systems Design and Implementation · 2013
123
cited
A Hardware Accelerator for Protocol Buffers
Micro · 2021
66
cited
FPGA Accelerated INDEL Realignment in the Cloud
International Symposium on High-Performance Computer Architecture · 2019
46
cited
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems
International Symposium on Computer Architecture · 2023
30
cited
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM
Symposium on Field Programmable Gate Arrays · 2019
30
cited
Profiling Hyperscale Big Data Processing
International Symposium on Computer Architecture · 2023
27
cited
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles
International Conference on Field-Programmable Logic and Applications · 2018
26
cited
FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design
International Conference on Architectural Support for Programming Languages and Operating Systems · 2020
23
cited
Vector Processors for Energy-Efficient Embedded Systems
MES@ISCA · 2016
20
cited
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · 2019
14
cited
Invited: Chipyard - An Integrated SoC Research and Implementation Environment
Design Automation Conference · 2020
12
cited
Hwacha Preliminary Evaluation Results, Version 3.8.1
2015
8
cited
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim
IEEE Micro · 2021
5
cited
Hwacha Preliminary Evaluation Results , Version 3 . 8
2015
5
cited
RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
2023
5
cited
FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs
International Symposium on Computer Architecture · 2024
4
cited
Sotabase
Sagar Karandikar | Researcher Profile | Sotabase | Sotabase