Sotabase

Career

· Co-Founder and Chief Architect, SiFive Inc.2015–
· Chief Architect / Chairman of the Board, RISC-V International2010–
· Professor of the Graduate School, University of California, Berkeley2007–
· Professor, Massachusetts Institute of Technology (MIT)1998–2007
· PhD in Computer Science, University of California, Berkeley1998–
· B.A. in Electrical and Information Sciences, University of Cambridge1987–
· BA in Electrical and Information Sciences, University of Cambridge, UK1987–

Publications (282)

The Landscape of Parallel Computing Research: A View from Berkeley
2006
2,450
cited
Single-chip microprocessor that communicates directly using light
Nature · 2015
1,170
cited
Chisel: Constructing hardware in a Scala embedded language
DAC Design Automation Conference 2012 · 2012
1,050
cited
The Rocket Chip Generator
2016
762
cited
Direction-optimizing Breadth-First Search
International Conference for High Performance Computing, Networking, Storage and Analysis · 2012
575
cited
The GAP Benchmark Suite
arXiv.org · 2015
574
cited
Unbounded transactional memory
International Symposium on High-Performance Computer Architecture · 2005
554
cited
Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology
International Conference on Supercomputing · 1997
505
cited
Keystone: an open framework for architecting trusted execution environments
European Conference on Computer Systems · 2020
463
cited
Energy-aware lossless data compression
TOCS · 2006
421
cited
Mondrian memory protection
ASPLOS X · 2002
347
cited
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors
International Symposium on Computer Architecture · 2005
344
cited
Reducing power density through activity migration
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. · 2003
342
cited
Silicon-photonic clos networks for global on-chip communication
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip · 2009
341
cited
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
IEEE Micro · 2020
315
cited
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
Design Automation Conference · 2019
307
cited
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
IEEE Symposium on High-Performance Interconnects · 2008
281
cited
PHANTOM: practical oblivious computation in a secure processor
Conference on Computer and Communications Security · 2013
263
cited
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
International Symposium on Computer Architecture · 2018
244
cited
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
IEEE Micro · 2009
227
cited
Sotabase
Krste Asanović | Researcher Profile | Sotabase | Sotabase