Sotabase

Career

· Hardware Engineer (Contract), Taalas2025–2025
· Research Intern, Google2024–2024
· FPGA Engineering Intern, Jane Street2023–2023
· Research Assistant, UC Berkeley2023–2025
· CPU Verification Intern, Apple2021–2021
· Research Intern (ASIC and VLSI Research Group), NVIDIA2018–2018
· PhD EECS, UC Berkeley2018–2025
· PhD Student, UC Berkeley2018–2025
· Research Assistant, UC Berkeley College of Engineering2018–2025
· Research Assistant, Berkeley Wireless Research Center2017–2017
· Digital Verification Intern, Analog Devices2016–2016
· TA for EECS 151 (Digital Design and Circuits), UC Berkeley2016–2017
· Intern, Guidewire Software2015–2016
· BS EECS, UC Berkeley2014–2018
· iOS/Web Application Developer, Zurich North America2014–2015
· Web Developer, California Educational Centers, Inc.2012–2014

Publications (11)

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
Design Automation Conference · 2019
307
cited
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures
arXiv.org · 2019
73
cited
Pattern Census: A Characterization of Pattern Usage in Early Programming Courses
Technical Symposium on Computer Science Education · 2021
16
cited
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020
15
cited
RTL-Repair: Fast Symbolic Repair of Hardware Design Code
International Conference on Architectural Support for Programming Languages and Operating Systems · 2024
14
cited
Simulator Independent Coverage for RTL Hardware Languages
International Conference on Architectural Support for Programming Languages and Operating Systems · 2023
9
cited
Early Diagnosis of Cataract and Diabetic Retinopathy for Rural India using a Cloud-Based Deep Learning Model
2023 International Conference on Advanced Computing Technologies and Applications (ICACTA) · 2023
3
cited
A Review of Emotion Detection Systems
International Conferences on Contemporary Computing and Informatics · 2022
2
cited
RTL bug localization through LTL specification mining (WIP)
International Conference on Formal Methods and Models for Co-Design · 2019
2
cited
MAVERIC: A 16nm 72 FPS, 10 mJ/Frame Heterogeneous Robotics SoC with 4 Cores and 13 INT8/FP32 Accelerators
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2025
1
cited
MAVERIC: A Heterogeneous Robotics SoC With 4 CPU Cores and 13 INT8/FP32 Accelerators in 16-nm-Class Technology
IEEE Journal of Solid-State Circuits · 2026
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Vighnesh Iyer | Researcher Profile | Sotabase | Sotabase