Sotabase

Career

· Distinguished Engineer, Infineon Technologies AG
· Collaborator/Contributor, Stanford University
· Professor, Technical University of Munich

Publications (181)

A Survey of Graph Neural Networks for Electronic Design Automation
Workshop on Machine Learning for CAD · 2021
75
cited
Industrial IP integration flows based on IP-XACT standards
Design, Automation and Test in Europe · 2008
57
cited
Safety evaluation of automotive electronics using Virtual Prototypes: State of the art and research challenges
Design Automation Conference · 2014
53
cited
Implementation of a Transaction Level Assertion Framework in SystemC
2007 Design, Automation & Test in Europe Conference & Exhibition · 2007
52
cited
Hardware-dependent Software: Principles and Practice
2009
51
cited
The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems
Design, Automation and Test in Europe · 2015
50
cited
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications
ACM Trans. Design Autom. Electr. Syst. · 2022
44
cited
Requirements and Concepts for Transaction Level Assertions
ICCD · 2006
31
cited
The Extendable Translating Instruction Set Simulator (ETISS) Interlinked with an MDA Framework for Fast RISC Prototyping
RSP · 2017
29
cited
Using VHDL for HW/SW co-specification
Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference · 1993
29
cited
The design cube-a model for VHDL designflow representation
European Design Automation Conference · 1992
28
cited
Design centric modeling of digital hardware
High Level Design Validation and Test Workshop · 2016
27
cited
The system verification methodology for advanced TLM verification
International Conference on Hardware/Software Codesign and System Synthesis · 2012
27
cited
Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead: Special Session Paper
International Conference on Hardware/Software Codesign and System Synthesis · 2021
26
cited
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2016
23
cited
Re-use-centric architecture for a fully accelerated testbench environment
Proceedings - Design Automation Conference · 2003
23
cited
Applying GNNs to Timing Estimation at RTL : (Invited Paper)
2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) · 2022
22
cited
Execution semantics and formalisms for multi-abstraction TLM assertions
Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings. · 2006
22
cited
Hardware/software Co-simulation In A Vhdl-based Test Bench Approach
Proceedings - Design Automation Conference · 1997
22
cited
The metamodeling approach to system level synthesis
Design, Automation and Test in Europe · 2014
22
cited
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