Sotabase

Career

· Program Manager, Siemens EDA2022–
· Staff Engineer Formal Verification and Methodology, Infineon Technologies2020–2022
· Formal Verification Engineer | PhD candidate, Infineon Technologies2017–2020
· Master Thesis, Infineon Technologies2016–2016
· Intern, Intel Corporation2015–2016
· Master of Science in Embedded Computing Systems, Technische Universität Kaiserslautern2014–2016
· Electrical and Computer engineer/ Associate Lecturer, Department of Technical Education, Government of Karnataka2012–2014
· Systems Engineer, Tata Consultancy Services2010–2012
· Bachelor of Engineering in Electronics and Communication Engineering, Visveswaraya Technological University2007–2010

Publications (0)

The Extendable Translating Instruction Set Simulator (ETISS) Interlinked with an MDA Framework for Fast RISC Prototyping
RSP · 2017
29
cited
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications
Euromicro Symposium on Digital Systems Design · 2018
20
cited
Gap-free Processor Verification by S2QED and Property Generation
Design, Automation and Test in Europe · 2020
16
cited
Meta-model Based Automation of Properties for Pre-Silicon Verification
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2018
14
cited
Formal Verification Methodology in an Industrial Setup
Euromicro Symposium on Digital Systems Design · 2019
13
cited
Embedded Systems’ Automation following OMG’s Model Driven Architecture Vision
Design, Automation and Test in Europe · 2019
12
cited
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study
Design, Automation and Test in Europe · 2019
12
cited
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation
IEEE transactions on computers · 2020
11
cited
Extending Verilator to Enable Fault Simulation
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen · 2021
10
cited
Python based framework for HDSLs with an underlying formal semantics: (Invited paper)
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · 2017
9
cited
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems · 2021
8
cited
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision
Design, Automation and Test in Europe · 2019
7
cited
On generation of properties from specification
High Level Design Validation and Test Workshop · 2017
6
cited
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications
Microprocessors and microsystems · 2019
6
cited
ISA Modeling with Trace Notation for Context Free Property Generation
Design Automation Conference · 2021
5
cited
How to Keep 4-Eyes Principle in a Design and Property Generation Flow
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen · 2019
4
cited
MetaFS: Model-driven Fault Simulation Framework
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems · 2022
4
cited
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) · 2019
4
cited
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2022
3
cited
Invited: Increasing Soft Error Resilience by Software
Design Automation Conference · 2019
3
cited
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