Sotabase

Career

· Associate Professor (Research), Computer Science, Stanford University2021–

Publications (18)

Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead: Special Session Paper
International Conference on Hardware/Software Codesign and System Synthesis · 2021
26
cited
RTL Delay Prediction Using Neural Networks
IEEE Nordic Circuits and Systems Conference · 2021
17
cited
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems · 2021
8
cited
ISA Modeling with Trace Notation for Context Free Property Generation
Design Automation Conference · 2021
5
cited
Early RTL delay prediction using neural networks
Microprocessors and microsystems · 2022
3
cited
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen · 2022
2
cited
Bits, Flips and RISCs
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems · 2023
2
cited
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
Design Automation Conference · 2023
2
cited
Optimized HW/FW Generation from an Abstract Register Interface Model
Euromicro Symposium on Digital Systems Design · 2020
2
cited
Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications
Euromicro Symposium on Digital Systems Design · 2023
2
cited
An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems · 2024
1
cited
Aspect-Oriented Design Automation with Model Transformation
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2021
1
cited
Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond
IEEE Nordic Circuits and Systems Conference · 2024
1
cited
HW-Acceleration for Edge-AI
2024
1
cited
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods
IEEE International Symposium on Quality Electronic Design · 2024
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions
International Conference / Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation · 2022
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen · 2023
Transformative Hardware Design Following the Model-Driven Architecture Vision
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2021
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Sebastian Prebeck | Researcher Profile | Sotabase | Sotabase