Sotabase

Career

· William E. Ayer Professor of Electrical Engineering and Professor of Computer Science, Stanford University2006–
· Principal Engineer, Intel Corporation2001–2005
· Ph.D. in Electrical Engineering, Stanford University2000–
· Master of Technology (M.Tech) in Computer Science, Indian Institute of Technology, Kharagpur1996–
· Undergraduate degree in Computer Science and Engineering, Jadavpur University1994–

Publications (372)

Carbon nanotube computer
Nature · 2013
911
cited
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
Nature · 2017
657
cited
The case for RAMClouds: scalable high-performance storage entirely in DRAM
OPSR · 2010
563
cited
Circuit Failure Prediction and Its Application to Transistor Aging
IEEE VLSI Test Symposium · 2007
481
cited
Addressing failures in exascale computing
The international journal of high performance computing applications · 2014
469
cited
ERSA: Error Resilient System Architecture for probabilistic applications
Design, Automation and Test in Europe · 2010
347
cited
Which concurrent error detection scheme to choose ?
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) · 2000
297
cited
Quantitative evaluation of soft error injection techniques for robust system design
Design Automation Conference · 2013
227
cited
Sequential Element Design With Built-In Soft Error Resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2006
222
cited
S: Error Detection by Diverse Data and Duplicated Instructions
2002
217
cited
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004
213
cited
X-compact: an efficient response compaction technique for test cost reduction
Proceedings. International Test Conference · 2002
213
cited
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
IEEE/ACM International Conference on Computer-Aided Design · 2008
196
cited
Energy-Efficient Abundant-Data Computing: The N3XT 1,000x
Computer · 2015
187
cited
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns
Design, Automation and Test in Europe · 2008
172
cited
Post-silicon validation opportunities, challenges and recent advances
Design Automation Conference · 2010
168
cited
Underdesigned and Opportunistic Computing in Presence of Hardware Variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2013
162
cited
Combinational Logic Soft Error Correction
2006 IEEE International Test Conference · 2006
158
cited
CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.
Nano letters (Print) · 2009
153
cited
Optimized Circuit Failure Prediction for Aging: Practicality and Promise
2008 IEEE International Test Conference · 2008
152
cited
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Subhasish Mitra | Researcher Profile | Sotabase | Sotabase