Sotabase

Career

· Professor, Yale University2019–

Publications (88)

CoScale: Coordinating CPU and Memory System DVFS in Server Systems
Micro · 2012
203
cited
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
International Symposium on Computer Architecture · 2009
199
cited
CoLT: Coalesced Large-Reach TLBs
Micro · 2012
198
cited
Nimble Page Management for Tiered Memory Systems
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
180
cited
Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces
International Conference on Architectural Support for Programming Languages and Operating Systems · 2013
169
cited
Increasing TLB reach by exploiting clustering in page translations
International Symposium on High-Performance Computer Architecture · 2014
151
cited
Shared last-level TLBs for chip multiprocessors
2011 IEEE 17th International Symposium on High Performance Computer Architecture · 2011
145
cited
Large pages and lightweight memory management in virtualized environments: Can you have it both ways?
Micro · 2015
120
cited
Large-reach memory management unit caches
Micro · 2013
114
cited
Efficient Address Translation for Architectures with Multiple Page Sizes
International Conference on Architectural Support for Programming Languages and Operating Systems · 2017
111
cited
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
International Conference on Parallel Architectures and Compilation Techniques · 2009
107
cited
MIND: In-Network Memory Management for Disaggregated Data Centers
Symposium on Operating Systems Principles · 2021
105
cited
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
IEEE International Symposium on Performance Analysis of Systems and Software · 2016
95
cited
Inter-core cooperative TLB for chip multiprocessors
ASPLOS XV · 2010
83
cited
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
International Conference on Architectural Support for Programming Languages and Operating Systems · 2019
75
cited
MultiScale: memory system DVFS with multiple memory controllers
International Symposium on Low Power Electronics and Design · 2012
72
cited
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs
TACO · 2013
70
cited
Translation Ranger: Operating System Support for Contiguity-Aware TLBs
International Symposium on Computer Architecture · 2019
70
cited
Translation-Triggered Prefetching
International Conference on Architectural Support for Programming Languages and Operating Systems · 2017
68
cited
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface
International Conference on Architectural Support for Programming Languages and Operating Systems · 2016
64
cited
Sotabase
Abhishek Bhattacharjee | Researcher Profile | Sotabase | Sotabase