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Career

· Assistant Professor, Microelectronics Thrust, The Hong Kong University of Science and Technology (Guangzhou)2021–
· M.A. in Electrical Engineering, Princeton University2017–
· Ph.D. in Electrical and Computer Engineering, Princeton University2017–2021
· B.S. in Microelectronics, Shanghai Jiao Tong University2015–

Publications (20)

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
113
cited
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
2024 IEEE LLM Aided Design Workshop (LAD) · 2023
111
cited
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
arXiv.org · 2024
57
cited
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
2024 IEEE LLM Aided Design Workshop (LAD) · 2024
50
cited
Instruction-Level Abstraction (ILA)
ACM Trans. Design Autom. Electr. Syst. · 2018
39
cited
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD) · 2023
38
cited
Pono: A Flexible and Extensible SMT-Based Model Checker
International Conference on Computer Aided Verification · 2021
36
cited
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions
International Conference on Tools and Algorithms for Construction and Analysis of Systems · 2019
18
cited
Synthesizing Environment Invariants for Modular Hardware Verification
International Conference on Verification, Model Checking and Abstract Interpretation · 2020
16
cited
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Design Automation Conference · 2024
15
cited
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification
Formal Methods in Computer-Aided Design · 2018
15
cited
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking
International Conference on Verification, Model Checking and Abstract Interpretation · 2021
12
cited
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
Asia and South Pacific Design Automation Conference · 2025
7
cited
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
7
cited
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) · 2021
6
cited
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Design Automation Conference · 2025
6
cited
AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction
Design, Automation and Test in Europe · 2024
1
cited
How Good is Your Property? A New Metric for Formal Property Coverage
2024 2nd International Symposium of Electronics Design Automation (ISEDA) · 2024
Word-Level Augmentation of Formal Proof by Learning from Simulation Traces
International Conference on Computer Aided Design · 2024
Word-Level Counterexample Reduction Methods for Hardware Verification
Design, Automation and Test in Europe · 2025
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