Sotabase

Career

· Asst. Prof., IIT Kanpur

Publications (42)

Evaluating the security of logic encryption algorithms
IEEE International Symposium on Hardware Oriented Security and Trust · 2015
699
cited
A Formal Foundation for Secure Remote Execution of Enclaves
IACR Cryptology ePrint Archive · 2017
144
cited
Functional Analysis Attacks on Logic Locking
IEEE Transactions on Information Forensics and Security · 2018
143
cited
Reverse Engineering Digital Circuits Using Structural and Functional Analyses
IEEE Transactions on Emerging Topics in Computing · 2014
135
cited
WordRev: Finding word-level structures in a sea of bit-level gates
IEEE International Symposium on Hardware Oriented Security and Trust · 2013
101
cited
Malware detection using machine learning based analysis of virtual memory access patterns
Design, Automation and Test in Europe · 2017
99
cited
Reverse engineering digital circuits using functional analysis
Design, Automation and Test in Europe · 2013
89
cited
A Formal Approach to Secure Speculation
IEEE Computer Security Foundations Symposium · 2019
73
cited
Template-based circuit understanding
Formal Methods in Computer-Aided Design · 2014
52
cited
1 Instruction-Level Abstraction ( ILA ) : A Uniform Specification for System-on-Chip ( SoC ) Verification
2018
47
cited
Formal verification of taint-propagation security properties in a commercial SoC design
Design, Automation and Test in Europe · 2014
47
cited
HyperFuzzing for SoC Security Validation
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) · 2020
45
cited
UCLID5: Integrating Modeling, Verification, Synthesis and Learning
International Conference on Formal Methods and Models for Co-Design · 2018
44
cited
Verifying information flow properties of firmware using symbolic execution
Design, Automation and Test in Europe · 2016
41
cited
All-SAT Using Minimal Blocking Clauses
2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems · 2014
40
cited
Instruction-Level Abstraction (ILA)
ACM Trans. Design Autom. Electr. Syst. · 2018
39
cited
Template-based synthesis of instruction-level abstractions for SoC verification
Formal Methods in Computer-Aided Design · 2015
35
cited
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
Design, Automation and Test in Europe · 2010
33
cited
A HARDWARE-EFFICIENT LOGARITHMIC MULTIPLIER WITH IMPROVED ACCURACY
2020
25
cited
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding
Dependable Systems and Networks · 2010
25
cited
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Pramod Subramanyan | Researcher Profile | Sotabase | Sotabase