Sotabase

Career

· MS in Computer Science, ETH Zurich2020–2023
· Student / Programme Doctorate at D-ITET, ETH Zurich
· Research Intern, Meta
· Bachelor of Science in Computer Science, ShanghaiTech University

Publications (33)

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
IEEE computer architecture letters · 2023
102
cited
A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
Micro · 2021
93
cited
RowPress: Amplifying Read Disturbance in Modern DRAM Chips
International Symposium on Computer Architecture · 2023
81
cited
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
International Symposium on Computer Architecture · 2021
72
cited
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
International Symposium on Computer Architecture · 2020
62
cited
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
Dependable Systems and Networks · 2022
55
cited
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Micro · 2022
53
cited
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2022
51
cited
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
International Symposium on Computer Architecture · 2021
33
cited
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
International Symposium on High-Performance Computer Architecture · 2024
25
cited
SpyHammer: Using RowHammer to Remotely Spy on Temperature
arXiv.org · 2022
24
cited
ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
USENIX Security Symposium · 2023
23
cited
PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System
International Conference on Parallel Architectures and Compilation Techniques · 2024
22
cited
An Experimental Analysis of RowHammer in HBM2 DRAM Chips
2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S) · 2023
21
cited
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
International Symposium on High-Performance Computer Architecture · 2025
19
cited
Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
Dependable Systems and Networks · 2023
18
cited
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
International Symposium on High-Performance Computer Architecture · 2024
18
cited
A Case for Transparent Reliability in DRAM Systems
arXiv.org · 2022
15
cited
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
arXiv.org · 2023
11
cited
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations
Micro · 2024
10
cited
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Haocong (Richard) Luo | Researcher Profile | Sotabase | Sotabase