Sotabase

Career

· Director of the Intel Research Pittsburgh Lab, Intel Corporation2004–2007
· Associate Professor, Computer Science Department, Carnegie Mellon University1997–2008
· Assistant Professor, Department of Electrical and Computer Engineering, University of Toronto1993–1997
· Computer Architect, Silicon Graphics, Inc. / MIPS Computer Systems1989–1993

Publications (143)

Design and evaluation of a compiler algorithm for prefetching
ASPLOS V · 1992
826
cited
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
Micro · 2017
597
cited
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization
Micro · 2013
462
cited
Compiler-based prefetching for recursive data structures
ASPLOS VII · 1996
433
cited
A scalable approach to thread-level speculation
Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) · 2000
413
cited
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing
International Conference on Parallel Architectures and Compilation Techniques · 2012
405
cited
Base-delta-immediate compression: Practical data compression for on-chip caches
International Conference on Parallel Architectures and Compilation Techniques · 2012
387
cited
The potential for using thread-level data speculation to facilitate automatic parallelization
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture · 1998
378
cited
Tolerating Latency Through Software-Controlled Prefetching in Shared-Memory Multiprocessors
J. Parallel Distributed Comput. · 1991
316
cited
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
International Conference on Parallel Processing · 1990
308
cited
Tolerating latency through software-controlled data prefetching
1994
260
cited
Improving hash join performance through prefetching
Proceedings / International Conference on Data Engineering · 2004
238
cited
Automatic compiler-inserted I/O prefetching for out-of-core applications
USENIX Symposium on Operating Systems Design and Implementation · 1996
230
cited
Comparative evaluation of latency reducing and tolerating techniques
[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture · 1991
226
cited
Fast Bulk Bitwise AND and OR in DRAM
IEEE computer architecture letters · 2015
223
cited
The STAMPede approach to thread-level speculation
TOCS · 2005
187
cited
Scheduling threads for constructive cache sharing on CMPs
ACM Symposium on Parallelism in Algorithms and Architectures · 2007
181
cited
Improving index performance through prefetching
ACM SIGMOD Conference · 2001
178
cited
Linearly compressed pages: A low-complexity, low-latency main memory compression framework
Micro · 2013
160
cited
Programmable Matter
Computer · 2005
156
cited
Sotabase
Todd Mowry | Researcher Profile | Sotabase | Sotabase