Sotabase

Career

· Motorola Solutions Foundation Professor, Georgia Institute of Technology2021–2021
· Steve W. Chaddick School Chair, Georgia Institute of Technology2021–
· ON Semiconductor Junior Professor, Georgia Institute of Technology2015–2019
· Associate Professor, Georgia Institute of Technology2013–2015
· Staff Scientist, Intel Corporation2008–2013
· Ph.D. in Electrical and Computer Engineering, Purdue University2007–
· Analog Circuit Designer / Researcher, Texas Instruments2007–2008
· B.E. in Electrical and Telecommunication Engineering, Jadavpur University2001–

Publications (340)

Carbon-nanotube-based voltage-mode multiple-valued logic design
IEEE transactions on nanotechnology · 2005
304
cited
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
IEEE Journal of Solid-State Circuits · 2011
271
cited
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004
205
cited
Masked Face Recognition for Secure Authentication
arXiv.org · 2020
191
cited
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006
191
cited
Synchronized charge oscillations in correlated electron systems
Scientific Reports · 2014
183
cited
Leakage Power Analysis and Reduction for Nanoscale Circuits
IEEE Micro · 2006
157
cited
Roadmap on emerging hardware and technology for machine learning
Nanotechnology · 2020
149
cited
An Ising Hamiltonian solver based on coupled stochastic phase-transition nano-oscillators
Nature Electronics · 2021
145
cited
Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits
IEEE Transactions on Circuits and Systems Part 1: Regular Papers · 2007
144
cited
TapeCache: a high density, energy efficient cache based on domain wall memory
International Symposium on Low Power Electronics and Design · 2012
143
cited
X-DeepSCA: Cross-Device Deep Learning Side Channel Attack*
Design Automation Conference · 2019
133
cited
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling
Proceedings - Design Automation Conference · 2003
129
cited
Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances
International Electron Devices Meeting · 2009
128
cited
Device optimization for digital subthreshold logic operation
IEEE Transactions on Electron Devices · 2005
114
cited
A Survey of FPGA-Based Robotic Computing
IEEE Circuits and Systems Magazine · 2020
113
cited
Vertex coloring of graphs via phase dynamics of coupled oscillatory networks
Scientific Reports · 2016
108
cited
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005
101
cited
All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits
IEEE transactions on power electronics · 2016
96
cited
The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction
IEEE design & test · 2016
90
cited
Sotabase
Arijit Raychowdhury | Researcher Profile | Sotabase | Sotabase