Sotabase

Career

· VP Of Engineering, Motivo, Inc.2015–2024
· PMTS DFM CAD Engineer, GLOBALFOUNDRIES2009–2015
· Bachelor’s Degree, Electrical Engineering, Caltech2008–2008
· Master’s Degree, Electrical Engineering and Computer Science, University of California, Berkeley2008–2008
· Senior Process Engineer, AMD2005–2009
· Doctor of Philosophy (Ph.D.), Electrical Engineering and Computer Science, University of California, Berkeley

Publications (28)

DRC Plus: augmenting standard DRC with pattern matching on 2D geometries
SPIE Advanced Lithography · 2007
66
cited
Developing DRC plus rules through 2D pattern extraction and clustering techniques
Advanced Lithography · 2009
39
cited
Lossless layout compression for maskless lithography systems
Advanced Lithography · 2000
29
cited
Reduced complexity compression algorithms for direct-write maskless lithography systems
SPIE Advanced Lithography · 2006
26
cited
Lossless compression of VLSI layout image data
IEEE Transactions on Image Processing · 2006
24
cited
Data Compression for Maskless Lithography Systems: Architecture, Algorithms and Implementation
2008
19
cited
Lossless compression techniques for maskless lithography data
SPIE Advanced Lithography · 2002
18
cited
Systematic data mining using a pattern database to accelerate yield ramp
Advanced Lithography · 2014
18
cited
32 nm logic patterning options with immersion lithography
SPIE Advanced Lithography · 2008
17
cited
Binary combinatorial coding
Data Compression Conference, 2003. Proceedings. DCC 2003 · 2003
15
cited
Advanced low-complexity compression for maskless lithography data
SPIE Advanced Lithography · 2004
11
cited
Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
Advanced Lithography · 2009
11
cited
22-nm-node technology active-layer patterning for planar transistor devices
2010
10
cited
Layout decompression chip for maskless lithography
SPIE Advanced Lithography · 2004
10
cited
Full-chip characterization of compression algorithms for direct-write maskless lithography systems
Advanced Lithography · 2009
9
cited
22 nm technology node active layer patterning for planar transistor devices
Advanced Lithography · 2009
6
cited
Binary Lossless Layout Compression Algorithms and Architectures for Direct-write Lithography Systems
2001
6
cited
Pattern matching for identifying and resolving non-decomposition-friendly designs for double patterning technology (DPT)
Advanced Lithography · 2013
6
cited
Systematic physical verification with topological patterns
Advanced Lithography · 2014
6
cited
Design layout analysis and DFM optimization using topological patterns
Advanced Lithography · 2015
5
cited
Sotabase
Vito Dai | Researcher Profile | Sotabase | Sotabase