Sotabase

Career

· Principal Member Of Technical Staff, AMD2022–
· System Architect, AMD2022–2022
· System Architect, Xilinx2019–2022
· Principal Research Engineer, ARM2013–2019
· summa cum laude, Technische Universität Dresden2013–2019
· Research Assistant, TU Dresden2013–2013
· Senior Software Engineer, Advanced Micro Devices2007–2012
· Research Assistant, University of Cambridge2004–2005
· Student Researcher, TU Dresden2002–2008

Publications (42)

The gem5 Simulator: Version 20.0+
arXiv.org · 2020
364
cited
Delegated persist ordering
Micro · 2016
125
cited
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
European Conference on Computer Systems · 2010
123
cited
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2017
97
cited
Language-level persistency
International Symposium on Computer Architecture · 2017
94
cited
Persistency for synchronization-free regions
ACM-SIGPLAN Symposium on Programming Language Design and Implementation · 2018
87
cited
Nucleus
ACM Transactions on Embedded Computing Systems · 2017
72
cited
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Micro · 2010
70
cited
dist-gem5: Distributed simulation of computer clusters
IEEE International Symposium on Performance Analysis of Systems and Software · 2017
52
cited
BRB: Mitigating Branch Predictor Side-Channels.
International Symposium on High-Performance Computer Architecture · 2019
48
cited
Software Wear Management for Persistent Memories
USENIX Conference on File and Storage Technologies · 2019
39
cited
Hardware-Validated CPU Performance and Energy Modelling
IEEE International Symposium on Performance Analysis of Systems and Software · 2018
37
cited
Relaxed Persist Ordering Using Strand Persistency
International Symposium on Computer Architecture · 2020
37
cited
The TURBO Diaries: Application-controlled Frequency Scaling Explained
USENIX Annual Technical Conference · 2014
33
cited
Exploring system performance using elastic traces: Fast, accurate and portable
International Conference / Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation · 2016
23
cited
Hardware acceleration for lock-free data structures and software-transactional memory
2008
22
cited
Empirical CPU power modelling and estimation in the gem5 simulator
International Workshop on Power and Timing Modeling, Optimization and Simulation · 2017
20
cited
Thermally-aware composite run-time CPU power models
International Workshop on Power and Timing Modeling, Optimization and Simulation · 2016
17
cited
From Lightweight Hardware Transactional Memory to Lightweight Lock
2011
13
cited
Quantify the performance overheads of PMDK
International Symposium on Memory Systems · 2018
10
cited
Sotabase
Stephan Diestelhorst | Researcher Profile | Sotabase | Sotabase