Sotabase

Career

· Professor of Computer Engineering, University of Cambridge Department of Computer Science and Technology2014–

Publications (112)

Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits
PLoS Comput. Biol. · 2010
402
cited
The CHERI capability model: Revisiting RISC in an age of risk
International Symposium on Computer Architecture · 2014
389
cited
CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization
IEEE Symposium on Security and Privacy · 2015
327
cited
Improving smart card security using self-timed circuits
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems · 2002
219
cited
A communication characterisation of Splash-2 and Parsec
IEEE International Symposium on Workload Characterization · 2009
206
cited
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators
Workshop on Cryptographic Hardware and Embedded Systems · 2009
203
cited
Point to point GALS interconnect
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems · 2002
140
cited
The design and implementation of a low-latency on-chip network
Asia and South Pacific Conference on Design Automation, 2006. · 2006
130
cited
Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation
2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines · 2012
112
cited
A Power and Energy Exploration of Network-on-Chip Architectures
ACM/IEEE International Symposium on Networks-on-Chips · 2007
101
cited
Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine
International Conference on Architectural Support for Programming Languages and Operating Systems · 2015
101
cited
Security Evaluation of Asynchronous Circuits
Workshop on Cryptographic Hardware and Embedded Systems · 2003
100
cited
RETROSPECTIVE: Low-Latency Virtual-Channel Routers for On-Chip Networks
2023
93
cited
Balanced self-checking asynchronous logic for smart card applications
Microprocessors and microsystems · 2003
89
cited
An Energy and Performance Exploration of Network-on-Chip Architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009
83
cited
CHERI Concentrate: Practical Compressed Capabilities
IEEE transactions on computers · 2019
76
cited
Demystifying Data-Driven and Pausible Clocking Schemes
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) · 2007
75
cited
Self calibrating clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design · 2000
75
cited
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
Micro · 2019
67
cited
Cornucopia: Temporal Safety for CHERI Heaps
IEEE Symposium on Security and Privacy · 2020
66
cited
Sotabase
Simon Moore | Researcher Profile | Sotabase | Sotabase