Sotabase

Career

· Institute Associate Professor, New York University2020–2014
· Assistant Professor, New York University2014–2020
· Assistant Professor, University of Waterloo2010–2014
· Post-doctoral Fellow, Carnegie Mellon University2009–2010
· Intern, AMD2007–2007

Publications (221)

BadNets: Identifying Vulnerabilities in the Machine Learning Model Supply Chain
arXiv.org · 2017
2,058
cited
BadNets: Evaluating Backdooring Attacks on Deep Neural Networks
IEEE Access · 2019
1,222
cited
Fine-Pruning: Defending Against Backdooring Attacks on Deep Neural Networks
International Symposium on Recent Advances in Intrusion Detection · 2018
1,212
cited
CompAct
ACM Transactions on Embedded Computing Systems · 2019
292
cited
VeriGen: A Large Language Model for Verilog Code Generation
ACM Trans. Design Autom. Electr. Syst. · 2023
287
cited
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Workshop on Machine Learning for CAD · 2023
267
cited
Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation
USENIX Security Symposium · 2013
203
cited
The EDA challenges in the dark silicon era
Design Automation Conference · 2014
201
cited
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Design, Automation and Test in Europe · 2022
195
cited
SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud
Neural Information Processing Systems · 2017
186
cited
Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes
Network and Distributed System Security Symposium · 2015
172
cited
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator
IEEE VLSI Test Symposium · 2018
144
cited
AutoChip: Automating HDL Generation Using LLM Feedback
arXiv.org · 2023
139
cited
Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants
USENIX Security Symposium · 2022
136
cited
ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Learning Accelerators
Design Automation Conference · 2018
127
cited
Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors
Design, Automation and Test in Europe · 2013
113
cited
DeepReDuce: ReLU Reduction for Fast Private Inference
International Conference on Machine Learning · 2021
103
cited
CryptoNAS: Private Inference on a ReLU Budget
Neural Information Processing Systems · 2020
99
cited
Verifiable ASICs
IEEE Symposium on Security and Privacy · 2016
78
cited
Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
IEEE design & test · 2019
77
cited
Sotabase
Siddharth Garg | Researcher Profile | Sotabase | Sotabase