Sotabase

Career

· Professor, University of Toronto2017–
· Associate Professor, University of Toronto2014–2017
· Assistant Professor, University of Toronto2009–2014
· Intern, IBM2006–2006
· Intern, Intel2004–2004
· Research Assistant, University of Wisconsin-Madison2002–2008

Publications (98)

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009
745
cited
RETROSPECTIVE: Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing
2023
356
cited
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
International Symposium on Computer Architecture · 2008
255
cited
On-Chip Networks
Synthesis Lectures on Computer Architecture · 2009
247
cited
DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip
International Symposium on Computer Architecture · 2011
190
cited
SCARAB: A single cycle adaptive routing and bufferless network
Micro · 2009
181
cited
Enabling interposer-based disintegration of multi-core processors
Micro · 2015
178
cited
Achieving predictable performance through better memory controller placement in many-core CMPs
International Symposium on Computer Architecture · 2009
166
cited
Load Value Approximation
Micro · 2014
160
cited
Circuit-Switched Coherence
ACM/IEEE International Symposium on Networks-on-Chips · 2008
154
cited
Doppelgänger: A cache for approximate computing
Micro · 2015
130
cited
Modular Routing Design for Chiplet-Based Systems
International Symposium on Computer Architecture · 2018
113
cited
SynFull: Synthetic traffic models capturing cache coherent behaviour
International Symposium on Computer Architecture · 2014
106
cited
Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks
International Conference on Supercomputing · 2016
104
cited
Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets
arXiv.org · 2015
102
cited
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
Micro · 2014
96
cited
Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip
IEEE International Symposium on High-Performance Comp Architecture · 2012
92
cited
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
2008 41st IEEE/ACM International Symposium on Microarchitecture · 2008
85
cited
An Evaluation of Server Consolidation Workloads for Multi-Core Designs
IEEE International Symposium on Workload Characterization · 2007
69
cited
Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip · 2012
57
cited
Sotabase
Natalie Enright Jerger | Researcher Profile | Sotabase | Sotabase