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Career

· Board Member, CVS Ferrari2025–

Publications (199)

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
IEEE Transactions on Parallel and Distributed Systems · 2005
618
cited
Xpipes: a network-on-chip architecture for gigascale systems-on-chip
IEEE Circuits and Systems Magazine · 2004
506
cited
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
J. VLSI Signal Process. · 2005
270
cited
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005
252
cited
Low power error resilient encoding for on-chip data buses
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition · 2002
195
cited
Analyzing on-chip communication in a MPSoC environment
Proceedings Design, Automation and Test in Europe Conference and Exhibition · 2004
193
cited
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study
Proceedings of the Design Automation & Test in Europe Conference · 2006
170
cited
Network-on-chip architectures and design methods
2005
160
cited
SystemC Cosimulation and Emulation of Multiprocessor SoC Designs
Computer · 2003
138
cited
A high-efficiency wind-flow energy harvester using micro turbine
SPEEDAM 2010 · 2010
114
cited
Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes
Symposium on Integrated Circuits and Systems Design · 2005
111
cited
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip · 2010
101
cited
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip
Proceedings of the Design Automation & Test in Europe Conference · 2006
101
cited
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
ICCD · 2003
92
cited
Performance Analysis of Arbitration Policies for SoC Communication Architectures
Design automation for embedded systems · 2003
81
cited
Designing Network On-Chip Architectures in the Nanoscale Era
2010
80
cited
Allocation and Scheduling for MPSoCs via decomposition and no-good generation
International Joint Conference on Artificial Intelligence · 2005
78
cited
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems
Design, Automation and Test in Europe · 2013
67
cited
Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs
Proceedings 21st International Conference on Computer Design · 2003
67
cited
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis
Design, Automation and Test in Europe · 2013
64
cited
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Davide Bertozzi | Researcher Profile | Sotabase | Sotabase