Sotabase

Career

· Assistant Professor, University of Wisconsin-Madison2021–
· Device Engineer, Maxim Integrated2019–2021
· Post-Doctoral Researcher, UC Santa Barbara2018–2019
· Graduate Teaching Assistant, UC Santa Barbara2015–2015
· Undergraduate Teaching Assistant, UC Santa Barbara2014–2014
· Graduate Student Researcher, UC Santa Barbara2013–2018
· Doctor of Philosophy (PhD), III-Nitride Electronic Devices, University of California, Santa Barbara2013–2018
· Undergraduate Researcher, Indian Institute of Technology, Kanpur2012–2013
· Undergraduate Researcher, Universiti Teknologi Malaysia2012–2012

Publications (65)

Nested conformal prediction and quantile out-of-bag ensemble methods
Pattern Recognition · 2019
139
cited
In Situ Oxide, GaN Interlayer-Based Vertical Trench MOSFET (OG-FET) on Bulk GaN substrates
IEEE Electron Device Letters · 2017
125
cited
Distribution-free binary classification: prediction sets, confidence intervals and calibration
Neural Information Processing Systems · 2020
92
cited
Single-cell multi-cohort dissection of the schizophrenia transcriptome
Science · 2022
82
cited
Demonstration of ultra-small ( 0.2%) for mini-displays
2021
66
cited
Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices
International Electron Devices Meeting · 2017
63
cited
OG-FET: An In-Situ ${O}$ xide, ${G}$ aN Interlayer-Based Vertical Trench MOSFET
IEEE Electron Device Letters · 2016
59
cited
Demonstration of ultra-small (<10 μm) 632 nm red InGaN micro-LEDs with useful on-wafer external quantum efficiency (>0.2%) for mini-displays
Applied Physics Express · 2020
50
cited
Distribution-free calibration guarantees for histogram binning without sample splitting
International Conference on Machine Learning · 2021
50
cited
Top-label calibration and multiclass-to-binary reductions
International Conference on Learning Representations · 2021
49
cited
Large-Area In-Situ Oxide, GaN Interlayer-Based Vertical Trench MOSFET (OG-FET)
IEEE Electron Device Letters · 2018
47
cited
Color-tunable <10 μm square InGaN micro-LEDs on compliant GaN-on-porous-GaN pseudo-substrates
2020
45
cited
High breakdown voltage p–n diodes on GaN on sapphire by MOCVD
2016
45
cited
Growth of strain-relaxed InGaN on micrometer-sized patterned compliant GaN pseudo-substrates
2020
41
cited
Fabrication of relaxed InGaN pseudo-substrates composed of micron-sized pattern arrays with high fill factors using porous GaN
Semiconductor Science and Technology · 2019
35
cited
Comparing electrical performance of GaN trench-gate MOSFETs with a-plane and m-plane sidewall channels
2016
34
cited
First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET
IEEE Electron Device Letters · 2017
30
cited
Compliant Micron-Sized Patterned InGaN Pseudo-Substrates Utilizing Porous GaN
Materials · 2020
28
cited
An improved methodology for extracting interface state density at Si3N4/GaN
2020
26
cited
Improved Dynamic RON of GaN Vertical Trench MOSFETs (OG-FETs) Using TMAH Wet Etch
IEEE Electron Device Letters · 2018
26
cited
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