Sotabase

Career

· Chief Executive Officer, Chohotech2019–
· ZJU100 Professor, Zhejiang University (ZJU)2017–
· Assistant Professor, ShanghaiTech University2015–2017
· Research Scholar, University College London - Department of Computer Science2013–2013
· Postdoctoral Research Associate, Yale University2013–2015
· Research Fellow, KAUST - Geometric Modeling and Scientific Visualization Center2011–2013
· Research Intern, Oregon State University - Department of Computer Science2011–2011
· Doctor of Philosophy (PhD), Computer Science, A, The Hong Kong University of Science and Technology2007–2011
· Software Engineering Intern, Autodesk2006–2006
· Master's degree, Mathematics and Computer Graphics, A, Zhejiang University2005–2007

Publications (35)

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization
IEEE International Solid-State Circuits Conference · 2021
38
cited
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models
IEEE International Solid-State Circuits Conference · 2024
27
cited
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications
IEEE International Solid-State Circuits Conference · 2024
24
cited
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization
IEEE Journal of Solid-State Circuits · 2023
18
cited
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling
Micro · 2024
17
cited
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design
IEEE Transactions on Circuits and Systems Part 1: Regular Papers · 2022
15
cited
Mineralization processes involved in the formation of the Jinya Carlin-type Au deposit, northwestern Guangxi, China: Evidence from in situ trace element and S isotope geochemistry of Au-bearing zoned pyrite
2021
13
cited
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition
IEEE Transactions on Circuits and Systems Part 1: Regular Papers · 2023
13
cited
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture
International Symposium on Computer Architecture · 2024
12
cited
14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-30 Loss for Compound AI
IEEE International Solid-State Circuits Conference · 2025
11
cited
7.7 CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction
IEEE International Solid-State Circuits Conference · 2023
10
cited
A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2023
10
cited
MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness
Proceedings of the 2025 58th IEEE/ACM International Symposium on Microarchitecture · 2025
7
cited
BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination
IEEE Transactions on Circuits and Systems - II - Express Briefs · 2025
6
cited
A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array
IEEE Journal of Solid-State Circuits · 2025
5
cited
Caledonian Tin Mineralization in the Jiuwandashan Area, Northern Guangxi, South China
Minerals · 2022
5
cited
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
Design Automation Conference · 2024
5
cited
15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch
IEEE International Solid-State Circuits Conference · 2024
3
cited
A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2024
3
cited
Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
IEEE Transactions on Circuits and Systems Part 1: Regular Papers · 2025
3
cited
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