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· National Instruments

Publications (17)

Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
International Conference on Computer Aided Verification · 2009
87
cited
Trace-Based Symbolic Analysis for Atomicity Violations
International Conference on Tools and Algorithms for Construction and Analysis of Systems · 2010
80
cited
On design and implementation of an embedded automatic speech recognition system
17th International Conference on VLSI Design. Proceedings. · 2004
37
cited
Correct and non-defensive glue design using abstract models
International Conference on Hardware/Software Codesign and System Synthesis · 2011
19
cited
Static dataflow with access patterns: Semantics and analysis
DAC Design Automation Conference 2012 · 2012
19
cited
Analysis techniques for static dataflow models with access patterns
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing · 2012
11
cited
From Streaming Models to FPGA Implementations ERSA ’ 12 Industrial Regular Paper
2013
8
cited
On the Computational Complexity of Satisfiability Solving for String Theories
arXiv.org · 2009
8
cited
Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware
Journal of Signal Processing Systems · 2015
8
cited
On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations
2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) · 2014
7
cited
Beaver : An SMT Solver for Quantifier-free Bit-vector Logic Rhishikesh Limaye Research Project
2010
4
cited
Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets
Embedded Systems Development, From Functional Models to Implementations · 2014
1
cited
Specification of precise timing in synchronous dataflow models
International Conference on Formal Methods and Models for Co-Design · 2016
1
cited
Symbolic predictive analysis for concurrent programs
Formal Aspects of Computing · 2011
1
cited
DMD 01 : System Level Modeling and Refinement Verification of the FLEET Architecture Mentor ( s ) :
2006
Early timing estimation for system-level design using FPGAs (abstract only)
Symposium on Field Programmable Gate Arrays · 2012
Tools for deploying dataflow models on FPGA targets
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing · 2012
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