Sotabase

Career

· Postdoctoral Research Fellow, Georgia Institute of Technology2017–2018
· Platform Architect, Apple
· Senior CPU Architect, NVIDIA
· NVIDIA

Publications (56)

High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
IEEE/ACM International Symposium on Low Power Electronics and Design · 2011
95
cited
A hybrid packet-circuit switched on-chip network based on SDM
2009 Design, Automation & Test in Europe Conference & Exhibition · 2009
69
cited
Exploiting Intra-Request Slack to Improve SSD Performance
International Conference on Architectural Support for Programming Languages and Operating Systems · 2017
62
cited
Exploring the Potentials of Parallel Garbage Collection in SSDs for Enterprise Storage Systems
International Conference for High Performance Computing, Networking, Storage and Analysis · 2016
59
cited
Sequoia: A High-Endurance NVM-Based Cache Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2016
57
cited
An efficient STT-RAM last level cache architecture for GPUs
Design Automation Conference · 2014
42
cited
Boosting Access Parallelism to PCM-Based Main Memory
International Symposium on Computer Architecture · 2016
39
cited
Performance Evaluation of Dynamic Page Allocation Strategies in SSDs
ACM Transactions on Modeling and Performance Evaluation of Computing Systems · 2016
38
cited
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization
IEEE transactions on computers · 2016
35
cited
Reducing access latency of MLC PCMs through line striping
International Symposium on Computer Architecture · 2014
33
cited
A Reliable 3D MLC PCM Architecture with Resistance Drift Predictor
2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks · 2014
28
cited
Re-NUCA: A Practical NUCA Architecture for ReRAM Based Last-Level Caches
IEEE International Parallel and Distributed Processing Symposium · 2016
25
cited
A morphable phase change memory architecture considering frequent zero values
ICCD · 2011
24
cited
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2010
24
cited
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
International Conference on VLSI Design · 2010
22
cited
Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories
Dependable Systems and Networks · 2017
19
cited
Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory
2017
17
cited
Unleashing the potentials of dynamism for page allocation strategies in SSDs
Measurement and Modeling of Computer Systems · 2014
17
cited
REMAP: a reliability/endurance mechanism for advancing PCM
International Symposium on Memory Systems · 2017
16
cited
A comprehensive power-performance model for NoCs with multi-flit channel buffers
International Conference on Supercomputing · 2009
15
cited
Sotabase
Mohammad Arjomand | Researcher Profile | Sotabase | Sotabase