Sotabase

Career

· Director, ΓΑΒ LAB - Knowledge and Uncertainty Research Laboratory (Current)2017–
· Associate Professor, University of Peloponnese2013–
· Doctor of Philosophy - PhD, Computer Science, National Technical University of Athens

Publications (121)

Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip
IEEE J. Sel. Areas Commun. · 1991
563
cited
Fast switching and fair control of congested flow in broadband networks
IEEE J. Sel. Areas Commun. · 1987
116
cited
Variable packet size buffered crossbar (CICQ) switches
IEEE International Conference on Communications · 2004
106
cited
Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks
IEEE/ACM Transactions on Networking · 2001
83
cited
Pipelined memory shared buffer for VLSI switches
Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication · 1995
77
cited
The HiPEAC Vision
2010
72
cited
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
Proceedings IEEE INFOCOM 2006. 25TH IEEE International Conference on Computer Communications · 2006
59
cited
EUROSERVER: Energy Efficient Node for European Micro-Servers
2014 17th Euromicro Conference on Digital System Design · 2014
56
cited
Approaching Ideal NoC Latency with Pre-Configured Routes
ACM/IEEE International Symposium on Networks-on-Chips · 2007
54
cited
Weighted fairness in buffered crossbar scheduling
Workshop on High Performance Switching and Routing, 2003, HPSR. · 2003
48
cited
Crossbar NoCs Are Scalable Beyond 100 Nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012
47
cited
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems
Euromicro Symposium on Digital Systems Design · 2016
46
cited
Variable-size multipacket segments in buffered crossbar (CICQ) architectures
IEEE International Conference on Communications, 2005. ICC 2005. 2005 · 2005
42
cited
A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip · 2010
39
cited
Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques
ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240) · 2001
37
cited
User-level DMA without operating system kernel modification
Proceedings Third International Symposium on High-Performance Computer Architecture · 1997
37
cited
Credit-flow-controlled ATM for MP interconnection: The ATLAS I single-chip ATM switch
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture · 1998
36
cited
Multiple priorities in a two-lane buffered crossbar
IEEE Global Telecommunications Conference, 2004. GLOBECOM '04. · 2004
36
cited
A RISCy approach to VLSI
CARN · 1982
35
cited
Secondary Storage Management for Web Proxies
USENIX Symposium on Internet Technologies and Systems · 1999
35
cited
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Manolis G.H. Katevenis | Researcher Profile | Sotabase | Sotabase