Sotabase

Career

· Assistant Professor, Yale University, Department of Electrical & Computer Engineering2025–

Publications (40)

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
International Symposium on High-Performance Computer Architecture · 2017
744
cited
DPATCH: An Adversarial Patch Attack on Object Detectors
SafeAI@AAAI · 2018
337
cited
A Survey of Accelerator Architectures for Deep Neural Networks
2020
321
cited
GraphR: Accelerating Graph Processing Using ReRAM
International Symposium on High-Performance Computer Architecture · 2017
276
cited
A spiking neuromorphic design with resistive crossbar
Design Automation Conference · 2015
133
cited
HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array
International Symposium on High-Performance Computer Architecture · 2019
110
cited
AtomLayer: A Universal ReRAM-Based CNN Accelerator with Atomic Layer Computation
Design Automation Conference · 2018
104
cited
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
Symposium on Field Programmable Gate Arrays · 2021
86
cited
MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · 2017
85
cited
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators
International Symposium on High-Performance Computer Architecture · 2020
68
cited
ReCom: An efficient resistive accelerator for compressed deep neural networks
Design, Automation and Test in Europe · 2018
65
cited
ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks
Asia and South Pacific Design Automation Conference · 2018
64
cited
GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures
International Symposium on Computer Architecture · 2020
60
cited
Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication
Design Automation Conference · 2021
57
cited
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design
ACM Transactions on Reconfigurable Technology and Systems · 2022
43
cited
ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM
Design Automation Conference · 2019
36
cited
ReRAM-based accelerator for deep learning
Design, Automation and Test in Europe · 2018
35
cited
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training
Design Automation Conference · 2020
25
cited
PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM
Asia and South Pacific Design Automation Conference · 2020
23
cited
DPatch: Attacking Object Detectors with Adversarial Patches
arXiv.org · 2018
22
cited
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Linghao Song | Researcher Profile | Sotabase | Sotabase