Sotabase

Career

· Lecturer, ETH Zurich
· Post-doctoral researcher, ICCS - NTUA
· Diploma in Electrical and Computer Engineering, National Technical University of Athens
· Ph.D. in Electrical and Computer Engineering, National Technical University of Athens
· Postdoctoral Researcher, National Technical University of Athens
· Postdoctoral Researcher, SAFARI Research Group, ETH Zurich

Publications (0)

An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
Journal of Signal Processing Systems · 2017
24
cited
VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019
22
cited
Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing
International Conference on Field-Programmable Logic and Applications · 2019
15
cited
A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines
Technologies · 2020
13
cited
EVOLVE: Towards Converging Big-Data, High-Performance and Cloud-Computing Worlds
Design, Automation and Test in Europe · 2022
10
cited
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
IEEE Computer Society Annual Symposium on VLSI · 2017
7
cited
GPU accelerated blockchain over key-value database transactions
IET Blockchain · 2022
7
cited
Optimizing SVM Classifier Through Approximate and High Level Synthesis Techniques
International Conference on Modern Circuits and Systems Technologies · 2019
7
cited
Auto-tuning Multi-GPU High-Fidelity Numerical Simulations for Urban Air Mobility
Design, Automation and Test in Europe · 2024
5
cited
GANDAFL: Dataflow Acceleration for Short Read Alignment on NGS Data
IEEE transactions on computers · 2022
5
cited
Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach
Design, Automation and Test in Europe · 2019
3
cited
MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem
International Conference on Supercomputing · 2025
3
cited
HLS code transformation strategies and directives exploration for FPGA accelerated ECG analysis
2016
2
cited
Exploration of GPU sharing policies under GEMM workloads
Software and Compilers for Embedded Systems · 2020
1
cited
FPGA Acceleration of Short Read Alignment
Heart · 2021
1
cited
A Design Flow Framework for Fully-Connected Neural Networks Rapid Prototyping
Coins · 2019
FPGA acceleration in EVOLVE’s Converged Cloud-HPC Infrastructure
International Conference on Field-Programmable Logic and Applications · 2021
GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
2026
High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images
IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip · 2022
Processing-in-memory for genomics workloads
arXiv.org · 2025
Sotabase