Sotabase

Career

· Co-founder, Vector 122001–
· Invited Professor (Sabbatical), PMC-Sierra1995–
· Professor, The University of British Columbia1989–
· Invited Professor, Edith Cowan University, Perth, Australia
· Invited Professor, University of Bordeaux I
· Invited Professor, University of Montpellier II

Publications (182)

Performance evaluation and design trade-offs for network-on-chip interconnect architectures
IEEE transactions on computers · 2005
932
cited
System-on-Chip: Reuse and Integration
Proceedings of the IEEE · 2006
285
cited
Design of a switch for network on chip applications
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. · 2003
216
cited
Design, synthesis, and test of networks on chips
IEEE Design & Test of Computers · 2005
195
cited
A Small-Window Moving Average-Based Fully Automated Baseline Estimation Method for Raman Spectra
Applied Spectroscopy · 2012
110
cited
BIST for network-on-chip interconnect infrastructures
IEEE VLSI Test Symposium · 2006
103
cited
On-line fault detection and location for NoC interconnects
IEEE International Symposium on On-Line Testing and Robust System Design · 2006
98
cited
Jitter models for the design and test of Gbps-speed serial interconnects
IEEE Design & Test of Computers · 2004
96
cited
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
IEEE Design & Test of Computers · 2005
91
cited
Testing Network-on-Chip Communication Fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007
83
cited
Embedded timing analysis: a soc infrastructure
IEEE Design & Test of Computers · 2002
79
cited
High-throughput switch-based interconnect for future SoCs
The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings. · 2003
63
cited
A scalable communication-centric SoC interconnect architecture
International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720) · 2004
62
cited
Timing analysis of network on chip architectures for MP-SoC platforms
Microelectronics Journal · 2005
62
cited
Methodologies and algorithms for testing switch-based NoC interconnects
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems · 2005
60
cited
An Effective BIST Scheme for ROM's
IEEE Trans. Computers · 1992
56
cited
A packet switching communication-based test access mechanism for system chips
IEEE European Test Workshop, 2001. · 2001
55
cited
Essential Fault-Tolerance Metrics for NoC Infrastructures
IEEE International Symposium on On-Line Testing and Robust System Design · 2007
55
cited
Towards Open Network-on-Chip Benchmarks
51
cited
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
ACM Great Lakes Symposium on VLSI · 2004
49
cited
Sotabase
André Ivanov | Researcher Profile | Sotabase | Sotabase