Sotabase

Career

· Founding Engineer, Across AI2025–

Publications (36)

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures
Design Automation Conference · 2013
127
cited
Qubit placement to minimize communication overhead in 2D quantum architectures
Asia and South Pacific Design Automation Conference · 2014
122
cited
FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices
IEEE Computer Society Annual Symposium on VLSI · 2014
88
cited
An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits
IEEE transactions on applied superconductivity · 2017
60
cited
Layout Optimization for Quantum Circuits with Linear Nearest Neighbor Architectures
IEEE Circuits and Systems Magazine · 2016
43
cited
5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes
IEEE Computer Society Annual Symposium on VLSI · 2014
35
cited
SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits
International Symposium on Circuits and Systems · 2018
35
cited
Pilot Register File: Energy Efficient Partitioned Register File for GPUs
International Symposium on High-Performance Computer Architecture · 2017
28
cited
Design of multiple fanout clock distribution network for rapid single flux quantum technology
Asia and South Pacific Design Automation Conference · 2017
21
cited
Design of Complex Rapid Single-Flux-Quantum Cells with Application to Logic Synthesis
International Symposium on Electronic Commerce · 2017
20
cited
Low write-energy STT-MRAMs using FinFET-based access transistors
ICCD · 2014
20
cited
Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits
Quantum Information Processing · 2014
19
cited
Reversible logic synthesis of k-input, m-output lookup tables
Design, Automation and Test in Europe · 2013
14
cited
Squash: a scalable quantum mapper considering ancilla sharing
ACM Great Lakes Symposium on VLSI · 2014
14
cited
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement
Design, Automation and Test in Europe · 2018
13
cited
An efficient timing analysis model for 6T FinFET SRAM using current-based method
IEEE International Symposium on Quality Electronic Design · 2016
10
cited
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques
Design, Automation and Test in Europe · 2016
10
cited
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework
Design Automation Conference · 2016
9
cited
Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing
Quantum information & computation · 2015
9
cited
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations
Asia and South Pacific Design Automation Conference · 2015
8
cited
Sotabase
Alireza Shafaei | Researcher Profile | Sotabase | Sotabase